In a multilayer printed circuit board, the interlayer connections are typically formed by drilling down through a dielectric layer of film to the next underlying circuit layer and coating the resulting via with a conductive plating. The prior art interlayer forming techniques used in making inter-layer connections between thin-film wiring layers on organic substrates (composed of materials such as epoxy resins) were based on drilling and/or etching the dielectric and plating the resulting via.
The prior art etching process is shown in FIG. 3 (a) to (g). In this method, a conductor layer 11 is formed on a substrate 10 having a dielectric layer (FIG. 3 (a)). Then, photoresist 12 is applied onto the conductor 11, selectively exposed and developed (FIG. 3 (b)). The conductor 11 is selectively etched to form the lower layer wiring circuit 13 on a desired portion (FIG. 3 (c)), and the remaining photoresist 12 is removed (FIG. 3 (d)). Above the lower layer wiring circuit 13, a dielectric layer 14, formed of, for example, a photosensitive resin, is deposited (FIG. 3 (e)), and a via 15 is formed by etching (dry etching or wet etching) or pattern exposure and development, to expose the lower layer wiring circuit 13 (FIG. 3 (f)). Then, by means of a film forming technique, such as electroless plating, evaporation, or sputtering, an upper layer wiring circuit 16 is deposited. The wiring circuit is positioned to be electrically in contact with the via 15 and the lower layer wiring circuit 13 (FIG. (g)). By repeating the dielectric layer forming and etching process, and the circuit forming process, and the circuit layer forming processes, a multi-layer wiring board is formed on the organic substrate.
Published Unexamined Japanese Patent Application No. 51-118390 describes that after forming a polyimide film on the surface of an aluminum wired substrate, an organic Al compound layer is formed on the surface of the polyimide film, and a part of the Al compound layer on the polyimide film is removed to form a through hole. A second conductor layer is formed in the through hole to form a predetermined multi-wiring structure.
Published Unexamined Japanese Patent Application No. 58-93298 describes that after forming a circuitization layer on a substrate, a resist layer is formed thereon to form a lower-layer wiring pattern. Then, the resist layer is removed and a through hole is formed, an inter-layer insulation film constituting multi-layer wiring is made from a polyimide based resin, a resist film is formed on the insulation layer, a connecting through hole is formed, and after removing the resist film, an upper layer wiring is formed on the insulation layer which has been bake processed.
Published Unexamined Japanese Patent Application No. 60-180197 describes the formation of a first circuitization layer on a dielectric substrate and the deposition of a photopolymer film on the wiring pattern. The photopolymer film is photo-set by exposure and developed to form a photo-set film with a via hole formed in a predetermined position. Then, by use of the photo-set film as an inter-layer insulation film, a second layer wiring pattern is formed on the inter-layer dielectric film and via-hole. Further, the processes after the formation of the photo-polymer film are repeated in turn to form a multi-layer wiring pattern.
In Published Unexamined Japanese Patent Application No. 61-121393 and Published Unexamined Japanese Patent Application No. 61-127196, what is described is that using the insulation layer etching method, a wiring pattern of materials such as copper and chromium is formed on the sputtering method, or evaporation method, and at the same time, the via hole portions is made conductive to electrically connect to the conductor pattern of the lower layer.
The plating method process is shown in FIG. 5 (a) to (h). In this process, a metal film for lower layer wiring circuit 103 is deposited by a film forming method such as sputtering on a substrate 101. The substrate 101 has been coated with polyimide resin, and a lower layer wiring circuit 103 is formed in turn through photosensitive resist coating, pattern exposure, developing, resist removing, and etching (FIG. 5 (a)).
Further, photosensitive resist 104 is coated on the lower layer wiring circuit 103 (FIG. 5 (b)), and a resist hole 105 is formed through pattern exposure of the photosensitive resist 104, developing, and resist removal (FIG. 5 (c)). In this resist hole 105, a plating via 106 is formed, for example, by electroplating (FIG. 5 (d)), and the resist is removed by use of predetermined solvent (FIG. 5 (e)). Then, the polyimide 107 is applied thereon (FIG. 5 (f)), and the surface of the polyimide is abraded flat to expose the top of the plating pillar 106 (FIG. 5 (g)), and an upper layer wiring circuit 108 is formed by a film forming technique such as sputtering thereon (FIG. 5 (h)). Multi-layer wiring is formed by repetition of these processes. Published Unexamined Japanese Patent Application No. 61-90496 describes a process in which a metal foil for a conductive circuit is configured and forms a lower layer wiring. Then, a polyimide film is formed and a resist hole is formed by mechanical drilling or by laser ablation in the position desired to form vias. Then, a plated via is formed in the resist hole by locally providing plating solution and laser beam.
Published Unexamined Japanese Patent Application No. 63-43396 describes a process for forming multi-layer wiring in which a lower layer of wiring is formed on the whole surface of a multi-layer wiring alumina substrate, and after a positive type dry film is pressure bonded, a resist pattern is formed through exposure and developing. A plated via is formed in the via hole by electroplating. Then, after removal of the plating resist pattern by solvent, an insulation layer is applied, the surface of the insulation layer is ground to expose the peak of the plated via, another insulation layer is applied thereon, a resist hole of desired diameter is formed in the resist layer, copper is sputter coated in the resist hole and on the surface of the above insulation layer, and a circuit pattern is formed by etching to obtain the multi-layer wiring.
Published Unexamined Japanese Patent Application No. 63-244797 describes a process in which a positive type dry film is laminated on an alumina substrate which has a lower-layer wiring pattern formed thereon, to form a resist pattern, and a resist hole for a plated via is formed through exposure and development. Then, the resist hole is subjected to copper sulfate plating to form a plated via, the above resist is removed by use of acetone, and a polyimide insulation layer is applied. Then, the surface of the insulation layer is ground to expose the head of the pillar. Then, a copper layer is deposited on the surface of the insulation layer and the head of the plating pillar with sputtering apparatus to form a desired wiring pattern.
Published Unexamined Japanese Patent Application No. 61-179598 describes a process in which a wiring pattern of copper is formed as the lower layer of wiring on a ceramic substrate, and on the surface of these, a photoresist pattern is formed by use of ordinary photolithographic technique. Then, the portions of the lower wiring layer surface exposed through the photoresist hole are electroplated to coat the plated vias. The whole surface of the above plating pillar and the exposed substrate is coated with polyimide resin, and impressed with a specified pressure from the surface of the dielectric layer toward the substrate, to make the dielectric layer surface flat. Then, an upper wiring layer is evaporated in a pattern on the insulation layer surface to form wiring.
Published Unexamined Japanese Patent Application No. 62-263645 describes a process in which a chrome layer and a copper layer are applied in turn on a substrate, etched and a predetermined pattern is formed. A positive photoresist is applied on the copper layer, and an opening section (resist hole) is formed through exposure and development of the resist. Then, the positive photoresist is sililated. The sililated resist remains as it is as a solder barrier, and forms a solder via bump in the above mentioned opening by a method such as dipping in a molten solder bath, and the upper-layer wiring is connected to it.
Published Examined Patent Application No. 50-2059 describes that an insulating substrate such as ceramic is coated with a copper layer thereon as a lower-layer wiring, a photoresist film is bonded thereon, a resist hole is formed when this resist is exposed to light and developed, and a conductive material such as copper is deposited in the hole by electro-plating. After the end of the electroplating, the residual photoresist is removed and an insulating material such as epoxy resin is deposited instead of it, and on the conductive material and the insulating material, a copper layer is electroless plated in order to effect interlayer connection.
The alignment between the lower wiring circuit and the via must be accurate in order to electrically connect the lower layer wiring and the upper layer wiring. According to the prior art dielectric layer patterning methods, since there is pattern aligning error between the lower layer wiring circuit and the via, the via diameter must be enlarged by as much as the possible error, or, as shown in FIG. 4, the size of the lower-layer electric circuit 13 must be larger than the diameter of resist hole 15 or plated via 106, and, thus, the electric circuit wiring density cannot be increased.
The prior art plated via method has a drawback such that when forming a plated via in the resist hole by removing the photosensitive resist which was once applied to form a circuit pattern, an additional process of applying resist and removing it again must be carried out.